There are many standards of data transmission for home use apparatuses. For example, an RF cable is used to transmit TV signals from an antenna to a TV. An S-Video is a data transmission standard to transmit TV signals. There is also another data transmission standard that transmits TV signals with split color components. All these standards transmit signals in analog waveforms. It is commonly known to a person skilled in the art that transmitting signals in analog waveforms creates noise.
In order to overcome such disadvantage and obtain high resolution images, several digital interfaces were introduced, e.g., Digital Visual Interface (DVI) or High-Definition Multimedia Interface (HDMI). The HDMI is the first interface that can carry uncompressed high definition video signals, compressed or uncompressed multi-channel audio signals, and intelligent format and command data. The HDMI specification can be backward compatible to the DVI. Also, tHDMI is highly demanded by movie makers who require protection to their intellectual properties. Moreover, HDMI allows users to control multiple consumer electronic devices with only one remote controller.
To communicate data between two devices digitally, there is a need for an accurate clock to synchronize data signals. There is usually a clock recovery circuit in the reception device that receives the clock from a transmitter device, generates an internal clock, and synchronizes the internal clock with the received clock. Therefore, the reception device can process and deliver the received data without errors. According to the HDMI specification, a clock recovery circuit needs not only to synchronize a received video clock but also to extract an audio clock according to the received video clock and few defined parameters, e.g., Cycle Time Stamp (CTS) and a factor parameter N.
In the pages 75-79 of the High-Definition Multimedia Interface Specification Version 1.2, published on Aug. 22, 2005 by HDMI Licensing, LLC, the requirements for audio sample clock capture and regeneration are defined. The disclosure of which is hereby incorporated herein by reference.
FIG. 1 illustrates an audio clock regeneration model according to the HDMI specification. A source device 11 transmits TMDS (Transmission Minimized Differential Signaling) or video clock to a sink device 12. Meanwhile, a parameter CTS and a parameter N are transmitted within an Audio Clock Regeneration Packet from the source device 11 to the sink device 12. In some video source devices, the audio and video clocks thereof are synchronized. There exists a rational (Integer divided by integer) relationship between these two clocks. In another situation, the audio and video clocks may be asynchronous. According to the HDMI specification, the sink device 12 shall still work in this environment and extract the fractional relationship between these two clocks.
The source device 11 shall first determine the fractional relationship between the video clock and an audio reference clock (128*fs) where fs is an audio sample rate. The source device contains a register 15, a divider 13, and a counter 14 wherein the register 15 keeps the parameter N, the divider 13 divides the audio reference clock by the parameter N, and the counter 14 counts the cycle time of the divided audio reference clock based on the video clock. The exact relationship between the two clocks is described in the following equation:128*fs=fTMDS—clock*N/CTS.
The source device 11 sends the numerator and denominator via the HDMI link to the sink device 12. Then, the clock recovery circuit of the sink device 12 includes a divider 16 and a frequency multiplier 17, wherein the divider 16 divides the incoming video (TMDS) clock by the parameter CTS, and the frequency multiplier 17 increases frequency of the divided video (TMDS) clock to N times the original frequency. Finally, a clock with a frequency in an audio frequency range and with synchronization of the received video clock is captured and regenerated.
FIG. 2 illustrates an optional architecture to implement an audio clock regeneration function that takes advantages of the N and CTS values. The frequency multiplier 17 is replaced by a conventional phase lock loop circuit including a phase detector 21, a low-pass filter 22, a VCO (Voltage Controlled Oscillator) 23, and a divider 24. It is well known to those skilled in the art that the conventional phase lock loop circuit can regenerate a synchronized clock. Therefore, the detailed operation of the conventional phase lock loop is ignored herein.
As mentioned in the page 76 of the HDMI specification, the difference in the parameter CTS, due to the asynchronous clocks, creates large jitter. Although the HDMI Specification recommended several N and CTS values, it is still difficult to obtain an audio clock with relatively low jitter. For example, to obtain an audio clock with 32 kHz from a video clock with 25.2 MHz, the parameter CTS would be 25,200 if the N parameter were 4096 as recommended in the HDMI specification. The received video (TMDS) clock in the sink device 12 was divided by the parameter CTS and reduced to 1 kHz before entering the phase lock loop circuit.
The phase lock loop circuit could not adjust itself with a low frequency input, e.g., 1 kHz. The phase detector 21 detects the phase change and forces the low-pass filter 22 to change its voltage level, such that the VCO 23 can send a feedback clock through the divider 24 to the phase detector 21, and update an output clock which is synchronized to the input clock, e.g., the 1 kHz clock. With such a low input clock, the phase lock loop circuit adjusts itself per 1 ms which is the period of a 1 kHz clock. Thus, the accurate requirement 1000 ppm of the HDMI specification can not be achieved easily because the phase lock loop circuit can only adjust its phase slowly and, moreover, noise may accumulate during this 1 ms waiting time.
The optional implementation of the clock recovery circuit in the sink device 12 according to the HDMI specification does not provide a low jitter clock recovery circuit. Therefore, it is an object of the present invention to provide a low jitter clock recovery circuit which also meets the requirements defined in the HDMI specification.